1. Field of the Invention
The invention relates to computer systems and more particularly to the graphics subsystem.
2. Description of the Related Art
Traditional personal computer architectures partition the computer system into the various blocks shown in the exemplary prior art system illustrated in FIG. 1. One feature of this prior art architecture is the use of the Peripheral Component Interconnect (PCI) bus 101 as the connection between the xe2x80x9cnorth bridgexe2x80x9d integrated circuit 103 and the xe2x80x9csouth bridgexe2x80x9d integrated circuit 105. North bridge 103 functions generally as a switch connecting CPU 107, a graphics bus 109 such as the Accelerated Graphics Port (AGP) bus, PCI bus 101 and main memory 111. North bridge 103 contains the memory controller function. The architecture also includes the xe2x80x9chost busxe2x80x9d connection 108 between north bridge 103 and CPU 107.
The south bridge 105 provides an interface to various input/output (I/O) portions of the computer system by providing, e.g., a bridge function between the PCI and legacy ISA bus 115, the Integrated Device Electronics (IDE) disk interface 117 and the Universal Serial Bus (USB) 119. Other devices, buses and functions may also be included in the South Bridge 105. In the illustrated prior art architecture, PCI bus 101 also functions as a major input/output bus for add-in functions such as network connection 121. The various busses and devices shown in FIG. 1 are conventional in the personal computer industry.
The exemplary graphics subsystem 123, illustrated in FIG. 1, couples to north bridge 103 over Accelerated Graphics Port (AGP) bus 109.
AGP 109 offloads graphics traffic from the PCI bus 101 and allows the graphics controller direct access to main memory 111 for graphics information (e.g. 3-D textures) stored in system memory. The graphics subsystem conventionally includes a graphics processor 124 for performing video calculations and video memory including frame buffer 125. The frame buffer provides a digital representation of the screen image. Video memory also typically includes memory storing data used in video calculations performed by the video processor. The size of video memory varies but typical graphics cards have memory on the order of e.g., 4-16 Mbytes. Another function provided by the graphics subsystem 123 is provided by the random access memory digital to analog converter (RAMDAC). The RAMDAC converts the digital representation of the screen stored in frame buffer 125 into analog data for display device 127. The RAMDAC may be for instance a 230 MHz RAMDAC with three 8 bit DACs providing the red, green and blue (RGB) signals to display 127.
One approach for providing lower cost personal computers is to provide an integrated graphics and northbridge function in order to try to reduce the number of system components. One disadvantage of such an approach is that the RAMDAC consumes a lot of power, e.g., on the order of 3W, making the power budget for the north bridge considerably higher than otherwise. Another cost savings approach, which may be used in conjunction with an integrated graphics and memory controller is to use system memory 111 for the video memory rather than providing for separate video memory. Such an approach is known as Unified Memory Architecture (UMA). The UMA approach can provide lower cost systems by eliminating separate video memory at the price of reduced graphics performance.
It would be desirable to reduce the cost of personal computers by providing a more highly integrated system without paying the penalty of high power consumption caused by the RAMDAC.
Accordingly, in one embodiment a computer system includes a first integrated circuit that has a central processing unit (CPU) and a graphics controller. An input/output integrated circuit, e.g., an I/O hub, which is coupled to a plurality of input/output buses, includes a RAMDAC. An communication link couples the first integrated circuit and the input/output integrated circuit and carries both graphics data to or from a frame buffer and also carries asynchronous system data between the processor and the input/output integrated circuit. The frame buffer may be located in the I/O hub, which further reduces graphics traffic over the communication link.
Another embodiment provides a method for communicating frame buffer data to an input/output integrated circuit that includes a RAMDAC, over a communication link connecting the input/output integrated circuit to a first integrated circuit that includes a graphics controller and a CPU. The method includes transferring frame buffer data from the first integrated circuit to the input/output integrated circuit over the communication link. The method further includes transferring input/output data between the CPU and the input/output integrated circuit over the communication link and transferring input/output data between the memory controller and the input/output integrated circuit over the communication link. If the frame buffer is located in the input/output integrated circuit, the frame buffer data is data written into the frame buffer. Otherwise, the frame buffer data is data being read from the frame buffer and provided to the input/output integrated circuit.